1. Field of the Invention
The present invention relates to a semiconductor device in which the surface of a circuit board thereof is resin-sealed together with a semiconductor chip thereof and, more particularly, to a semiconductor device that restrains degradation of the reliability of the semiconductor device by resin sealing.
2. Description of the Related Art
With the trend toward a thinner semiconductor device with more pins, there has been proposed a semiconductor device having a ball grid array (BGA) structure (hereinafter referred to as the “BGA type semiconductor device”). In the BGA type semiconductor device, a semiconductor chip is mounted on a circuit board, and solder balls provided on the circuit board serve as external connection terminals. This arrangement makes it possible to control the thickness of the package to about the thickness of the circuit board and to allow numerous solder balls to be arranged at high density, thus permitting the demand for a reduced thickness and an increased number of pins to be met. An example of such a BGA type semiconductor device with solder balls arranged on the rear surface of the circuit board thereof is disclosed in, for instance, Japanese Unexamined Patent Publication No. 11-317472 or Japanese Unexamined Patent Publication No. 9-219470. Regarding these BGA type semiconductor devices, a problem is described in that a molding resin runs off through a gap between a metal mold and a wiring board in the vicinity of a visible outline (molding line) of a molding resin layer in the peripheral portion of the circuit board, and resin burrs occur, adversely affecting the step for cutting the circuit board to for each semiconductor device. To restrain the occurrence of the resin burrs, according to the art disclosed in the former publication, solder resists 1 and 2 are layered along the molding line, as shown in FIG. 1, and the gap between the circuit board and the metal mold is closed by a solder resist 3 formed of the two layers so as to prevent the resin from leaking out. According to the art disclosed in the latter publication, a dam frame 12 constructed of a dummy wire and a resin layer or only a resin layer is formed along a molding line, as shown in FIG. 2, and the gap between a circuit board 11 and a cope 14 is closed by the dam frame 12 so as to prevent a resin 13 from leaking out.
However, the art in which the laminated solder resist or the dam frame is formed to close the gap between the circuit board and the metal mold requires the step for forming such a laminated solder resist or dam frame, leading to increased cost of the semiconductor device attributable to the additional step. Furthermore, unless the laminated solder resist or the dam frame is formed along the molding line of a sealing resin, the leakage of a resin cannot be effectively prevented. For this reason, therefore, it is necessary to position the laminated solder resist or the dam frame with high accuracy to form them. A smaller semiconductor device, in particular, requires high positioning accuracy, making it more difficult to fabricate the semiconductor device and also making the manufacturing process more complicated.
In recent years, there has been proposed a semiconductor device in which solder balls are disposed on the front surface of the circuit board thereof so as to allow a heat spreader or a heat sink to be disposed on the rear surface of the circuit board, thereby enhancing the heat radiation performance of the semiconductor device to improve the characteristics of the semiconductor device. Such a semiconductor device is referred to as an enhanced ball grid array (EBGA). In the present specification, the device is referred to as an advanced ball grid array type semiconductor device (ABGA).
FIG. 3 is a partially cutaway top plan view showing a conventional ABGA type semiconductor device; FIG. 4 is an enlarged top plan view of an area S2 of the ABGA type semiconductor device shown in FIG. 3; and FIG. 5 is an enlarged sectional view of the area S2, a part of which along the line D-D shown in FIG. 4 has been omitted. A circuit board 401 formed of multiple layers, the details of which are omitted, is attached onto the front surface of a heat spreader composed of a metal plate material, not shown, and a semiconductor chip 405 is mounted on the front surface of the heat spreader in an opening 411 provided at the center of the circuit board. The semiconductor chip 405 is electrically connected by bonding wires 406 to a bonding pad 426 formed on one end of each of multiple wiring patterns HP constructed of a wiring layer 421 formed on the front surface of the circuit board 401. The wiring layer 421 is electrically connected to a wiring layer, not shown, under the circuit board 401 via through holes 425, and also insulatively covered by a solder resist 415 provided on the front surface of the circuit board 401. In addition, a sealing resin 403 is molded to cover the semiconductor chip 405, the bonding wires 406, etc. To perform the molding, the circuit board 401 on which the semiconductor chip 405 has been mounted as described above is set on a resin molding apparatus, a metal mold is disposed so as to vertically clamp the circuit board 401, and a sealing resin is injected into the metal mold and cured, thus effecting the molding. A ball pad 427 formed on the other end of each of the wiring patterns HP is disposed in the peripheral portion of the front surface of the circuit board 401, which is free of the sealing resin 403 of the circuit board 401. Solder balls 404 are formed on the ball pad 427.
The conventional ABGA type semiconductor device set forth has been posing the following problems. First, during the molding of the sealing resin 403, a part of the resin flows out along the front surface of the circuit board 401 to the peripheral portion thereof and cures. Hence, as shown in FIG. 3 illustrating an example, a resin burr X facing toward the outer periphery occurs from a molding line ML, which is the external line of the sealing resin and which coincides with the line along the above line D-D in this case. Especially if the resin flows out to the area wherein the ball pads 427 are formed, the resin burrs X will be formed on the front surface of the ball pads 427. If such resin burrs are produced, the resin burrs X prevents metal materials for forming the solder balls 404 from being formed on the surfaces of the ball pads 427 in the step for forming the solder balls 404 on the ball pads 427. Even if the solder balls 404 are formed, the solder balls 404 may come off during a subsequent step or during transportation or the like.
Second, when the molding of the sealing resin 403 is carried out, in the portion along the visible outline of the sealing resin 403, that is, the molding line ML, the wiring layer 421 constituting the wiring patterns HP is crushed in the direction of the thickness and the wiring layer 421 may be disconnected in an extreme case.
Thus, the conventional ABGA type semiconductor device as been presenting a problem in that defects such as poor connection of the solder balls, the disconnection of the wiring layer, or the like takes place, resulting in a lower manufacturing yield of the semiconductor devices and degraded reliability of the semiconductor devices.
The present inventor has studied to identify the causes for such problems, and found the following. Referring back to FIG. 3 showing the conventional ABGA type semiconductor device, the multiple wiring patterns HP formed on the front surface of the circuit board are linearly extended between the wiring layers so as to minimize the wiring length between the bonding pads 426, which are connected by the bonding wires 406 to the semiconductor chip 405, and the ball pads 427 whereon the solder balls 404 are to be formed. There is a difference in the number of the wiring patters HP per unit area between the areas along the four sides and the areas in the four corners of the rectangular circuit board 401. In general, more ball pads can be formed in the areas at the four corners, so that more wire patterns HP are formed. For these reasons, in the case of the configuration example shown in FIG. 6, wiring patterns HP11 through HP15 will have a dense area wherein adjacent wiring patterns have a small interval dimension d1 and a sparse area wherein adjacent wiring patterns have a large interval dimension d2. As a result, in contrast to the area wherein the wiring patterns HP11 through HP15 are dense, the front surface of the solder resist 415 in the area wherein the wiring patterns are sparse is relatively concaved on the front surface of the circuit board 401, as shown in FIG. 3.
Accordingly, the circuit board having the solder resist 415 with the uneven surface due to the uneven density of the wiring patterns poses the problem described below when sealing the semiconductor chip or the like mounted thereon by a sealing resin. As shown by the sectional view of FIG. 6 taken along the same molding line ML as that shown in FIG. 5, when the circuit board is clamped between a cope UK and a drag DK in a resin molding apparatus, the solder resist 415 is slightly crushed and become even in the area wherein the wiring patterns are dense, bringing the front surface of the solder resist 415 into close contact with the cope UK, while a gap SP is produced between the front surface of the solder resist 415 and the cope UK in the area wherein the wiring patterns are sparse. Hence, when a resin is injected into the cavity of the metal mold to effect the molding, a part of the resin leaks out beyond a sealing area through the gap SP, and flows out beyond the molding line ML on the circuit board 401 as mentioned above into the area of the neighboring ball pads 427. The resin leaking out turns into the resin burr X when it cures.
There is another problem. At the time of the sealing resin molding, when circuit board is clamped between the cope UK and the drag DK, the clamping force causes the circuit board 401 to be subjected to a load in the direction of the thickness thereof. At this time, the load is dispersed to many wiring patterns in the area wherein the wiring patterns HP are dense, so that the load applied to each wiring pattern is reduced, while the load applied to each wiring pattern is relatively higher in the area wherein the wiring patterns are sparse, because the load is scattered less in the sparse area. Therefore, the wiring patterns in the area with sparse wiring patterns will be crushed in the direction of the thickness thereof by the load, resulting in a reduced thickness of the wiring patterns. This leads to an increase in the electrical resistance or disconnected wiring patterns in some cases.